Getting a logic-gate-level netlist from a GDS is trivial with industry standard chip design tools. Circuit designers do this every day. The hardest part will be reverse engineering the functionality.
I wish I had more time and I'd throw Calibre at it.
At my uni, 15 years ago, one postdoc reverse engineered NVIDIA chip and wrote more performant compiler. He did that by connecting oscyloscops to all chip's outputs and started with applying random current on inputs. Using ML and his genius he rediscoverd all opcodes including a few hidden ones. Eventually he got hired by some company that was doing a lot of GPU on supercomputers.
You can't do that by applying random inputs to any single-chip GPU - it has far too much state. I can see that perhaps it worked on some of the early multi-chip cards - where one chip was a texture sampler, and so on.
You'll have more luck reverse engineering the software driver first. They're not hidden, you can just open the driver files in Ghidra, the almost-universal tool for open-sourcing proprietary code. Hidden opcodes can be discovered first by just trying all the opcodes you couldn't discover any other way. You only need to go to the physical level if they're really hidden.
To be fair, Ghidra was released in 2019 and in general knowledge was still hard to find even back in 2010 I feel (well, compared to 2026 in the age of AI)
Before that there was, and still is, IDA Pro. Works largely the same but costs a lot, on the order of $1000/seat/year. Useless for hobbyists unless pirated, but reasonable if it's your job. Probably had academic discounts.
Also a few free-but-cut-down versions like 5 (which still recognizes MS-DOS executables). I'm not going to recommend downloading it from any of the locations mentioned here but it's out there: https://reverseengineering.stackexchange.com/questions/19179...
There is absolutely no way that happened. 15 years ago, we're talking Fermi class GPUs and chips with hundreds of millions of bits of on-chip state and much more if you include the DRAM.
You can't tease out the right information by applying random inputs. Which input would you even use? The PCIe interface? You'd first "randomly" need to get past its complex training sequences...
Your postdoc probably wrote micro-benchmarks of some sort. That is a common technique.
And you don't use an o-scope in anycase, since you'd need...what...a thousand of them to watch all the signals. You'd use a logic analyzer. I think I read somewhere that those older nvidia chips had something like 2000 BGA balls, and Tektronix does make an LA that can scale to 2000-something channels (TLA7000), for a modest US$500k or so. Then you gotta figure how to mount the thing to attach the probes.
So...agreed...far more likely there was a software solution of some kind if this happened.
Yes. There is exactly that, and we call it an "extraction" tool. It takes a GDS (text representation of shapes in the physical layout), and gives you back a "netlist" (text representation of components and connections in a circuit schematic).
Circuit designers use these tools basically daily for two reasons - the first is Layout Versus Schematic. We want to make sure that the physical layout matches the schematic, so the tool turns the layout GDS into a netlist and compares that to the netlist created from the schematic (basically a diff, but more complicated). The second is so we can run simulations that take into account the "parasitic" resistances and capacitances of the wires and metal shapes in the physical layout. It's basically the same procedure as LVS with an extra step that analyzes the metal shapes to determine said R's and C's.
Practically No, the stack-up of metal layers often hides the gate structures underneath, and the billions of process cells may not all be the same.
Theoretically Yes, as an ion-beam-mill and electron-microscope combination machine can slice up semiconductors layer-by-layer. Given these machines can often also give precise x-ray analysis material data, the exact makeup of the chip can be extracted by competitors given enough time. =3
I was thinking of the kind of high-energy photon sources that sprawl across a large laboratory campus behind rings of security fences.
These things can definitely erode the targets. Tomography experiments have to think carefully to optimize the set exposure angles used during a session, because the target degrades more with each shot.
From where do I know the name Dragon Sector and q3k? You aren't the ones who hacked the train DRM, are you? Or maybe active in the demo scene? Or maybe I'm just confusing you with TRSi?
I wish I had more time and I'd throw Calibre at it.
Rapid Chip Reverse Engineering Using Laser, Focused ion beams, and Scanning electron microscope https://academic.oup.com/mam/article/30/Supplement_1/ozae044...
FIBs are also used to test modifications before doing a respin. I'm still in awe that matter can be manipulated so precisely
This is absolutely not how reverse engineering a digital logic ASIC works.
Either the story got embellished through retellings, or this person was a fantasist.
There are people who hack on GPUs but it’s done at the software level.
You'll have more luck reverse engineering the software driver first. They're not hidden, you can just open the driver files in Ghidra, the almost-universal tool for open-sourcing proprietary code. Hidden opcodes can be discovered first by just trying all the opcodes you couldn't discover any other way. You only need to go to the physical level if they're really hidden.
You can't tease out the right information by applying random inputs. Which input would you even use? The PCIe interface? You'd first "randomly" need to get past its complex training sequences...
Your postdoc probably wrote micro-benchmarks of some sort. That is a common technique.
So...agreed...far more likely there was a software solution of some kind if this happened.
Circuit designers use these tools basically daily for two reasons - the first is Layout Versus Schematic. We want to make sure that the physical layout matches the schematic, so the tool turns the layout GDS into a netlist and compares that to the netlist created from the schematic (basically a diff, but more complicated). The second is so we can run simulations that take into account the "parasitic" resistances and capacitances of the wires and metal shapes in the physical layout. It's basically the same procedure as LVS with an extra step that analyzes the metal shapes to determine said R's and C's.
Theoretically Yes, as an ion-beam-mill and electron-microscope combination machine can slice up semiconductors layer-by-layer. Given these machines can often also give precise x-ray analysis material data, the exact makeup of the chip can be extracted by competitors given enough time. =3
Or maybe some kind of hybrid of x-ray microtomography and spectroscopic analysis all in one.
But, maybe the energies involved would be about the same destructive power as some microtome slicing technique...
These things can definitely erode the targets. Tomography experiments have to think carefully to optimize the set exposure angles used during a session, because the target degrades more with each shot.
https://www.chu.berkeley.edu/modern-semiconductor-devices-fo...
LLMs have already been shown to cause cognitive/skill performance losses in some users. =3
https://www.youtube.com/watch?v=axOcn--n_lM
I was waiting for some writeup about permutation decyphering
https://blog.dragonsector.pl/2017/10/?m=1
but reminds me how we're going to find out on an industrial level when the Saudis give China some nvidia chips they were grifted
they've cloned lots of chips before but nothing that advanced